Cavium S1 & Comm Semi Notes

I’ve posted/deleted/posted/deleted/posted this a few times this week ’cause I’m figuring my opinion may “rattle some cages” a little too hard. Such is life … Here goes ….

I’m a little late with this … … hat tip to Andrew@Nyquist for highlighting its existence … they filed in Feb, but better late than never πŸ˜‰ My blog searches have turned up very little on this, so I’m still the first to comment. Wonder if anyone really cares? I’m also pretty hesitant after all the “interesting” mail that WR Koss got on his Infinera and Clearwire posts.

I was curious when they set up shop in 2000 because they are part of the trend towards more f/w than h/w in semi products. It has been tough to follow their progress over the years. I don’t know any of them closely, but I worked with some of these guys for a few months back in the ’90’s. Getting “under the hood” with the S1 was an interesting exercise.

Anatomy of the new chip company Previously I’ve written about how semiconductor development is trending towards more and more firmware vs fixed functioned design (iPhone as Bellweather for Semiconductors & Commodity Computing, Still the King — I say “No Kidding :-(”. I’m guessing that Cavium is a “poster child” for this trend & thus I find it interesting that they don’t break down the 107 engineers into h/w and s/w. The text focusses on chips, but these are very s/w centric solutions. I’m guessing that they have a breakdown of something like 25% h/w and 75% s/w.

In the past few years companies, like bluetooth processor guys Cambridge Silicon Radio, have made great businesses doing it this way. Many Broadcom products are very similar in the h/w to s/w content. It can be done if one avoids proprietary processors and stays near the consumer space where the “system is reasonably small”.

Their Story — I completely believe that networking profits are going to be found in the “application processing” space that they note. I totally believe that “open-ish” CPUs, like MIPs & ARM, need to be used, that there is loads of software to be written ( IETF RFC’s don’t fit into ASICs very well … they do like SoCs), and that the development eco-systems are required. Cavium appears to be doing all the right things on the story front.

Forecast — The S1 doesn’t help convince me that chip companies can be profitable in this space. I’ve taken a quick scan of the Cavium S1 and it pains me to see that in their 7th year of existence (2000 to 2007) they are yet to be profitable, have an accumulated loss of ~ $61M, and have a paltry $34M 2006 Revenue. There is a possible hockey stick in the making here, but the past history of other security vendors like HiFn and SafeNet make me wary of a continued hockey stick. There is no debating that their last 3 years revenue is exciting. But its not clear to me that it will continue, or more specifically if it is enough.

Competition —They note the usual suspects which is fine for consumer segments. In bigger systems I believe their competition is in house software developed on a “Sea of DSPs” or “Sea of vanilla CPUs”.

Mkt Share — There is very little information on market share other than comparing their 2006 revenue of $34M to the iSuppli $5.8B for 2006 growing to $8.3B in 2010 for logic ASSPs. This is tiny. It also resonates with my back of the envelope calculations. For example, in this segment box revenue is usually 5 to 10x chip cost, so 2006 translates into $340M in box revenue. Which means that the box market-share of Cavium-based products is very low. The good news is that they have lots of room to grow.

Investors The Captital blog has done a cool analysis, capitalBLOG »Cavium Networks IPO Filing: Purple Rain? that indicates that Cavium’s Executive team has very little public company experience. All the VCs and key executives have much more experience in M&A.

Why does it cost so much when all you’re doing is piecing together “IP” to make an SoC, or NPU? The challenge, or gotcha, for all “network processor” companies from LSI ATMizer, Maker onward has been that the semi-vendor has had to do a lot of the software to win designs. That sounds okay except that the ratio of h/w to s/w in networking equipment is 4x+ ( that means for every unit of h/w effort there is 4 or more units of s/w effort ). Thus the development cost can, and often did/does, go zoom for an NPU vendor trying to win a design. There is also the issue of competing with the customer. This issue is relatively small in the consumer segment and grows more complex as the system gets bigger.

R&D — Overall I think development cost is the biggest issue for chip companies. The S1 indicates that Cavium is winning “Name” customers, Gross Margins are ok, but the R&D line is big. In the “hallway” this is often referred to as the “The Curse of Moore’s Law”. You can & have to put double the transistors on a chip every 2 years. Cool 😎 But end markets aren’t doubling and often there is a need for double the engineers to develop those transistors into something useful. This can be a “big” ouch. Cavium is no different here. It affects all semi players and hence the “herd like movement” towards “volume” markets that can support these costs.

How much funding does it take? — In the box world WR Koss has been wondering about ~300M in funding. In the semi-world I’m wondering about the >$60M in funding for Cavium, Wintegra, and Ample. ( Hell Cisco paid ~$90M for Skystone in ’97.) Historically, a $1B network box market has translated into a $100 – $200M semi ASSP market. The bottom line is that $60M in chip development requires a “beefy” box market, upping that by another ~$80M requires more.

Good Luck Cavium — I wish these guys the best of luck, they’ve done some great work in a very tough business. Cheers guys πŸ™‚ (extra — Clearwire got their cash this week so it appears the market is willing to accept “risk”.)

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