The Cavium posts were my first stab at reviewing a company in a public space. Lots of people enjoyed them, they were easily among the most popular posts here on my blog. Only the What the !@#$ Market Do? series has had more hits.
I received plenty of comments via e-mail. The following comment was so good that I asked if I could post it. I got a yes ( with some edits). Here it is:
I would call this the NPU two-step. We’ve seen it before:
* ATOMIZER I & II, PowerQUICC I & II (III finally), Maker SWAN (155 & 622), Intel IXP,. Moto C-PORT, and the list goes on.
The basic problem as I see it is this:
* In the 1st gen the NPU vendor designs an architecture that will scale nicely (read no SW changes) into the next node of technology. The marketing aggressively sells the capabilities to the point that the technology port is actually required to deliver so the 2nd gen (the two-step) is secured & everyone parties.
* Now we come to the third gen of technology and the NPU vendor is faced with a serious dilemma. Technology has advanced so far that many architectural decisions are no longer valid.
* Therefore, the NPU dude has to reset the architecture and (unlike an ISA where SW costs are distributed) bear the burden of changing all the tools, probably introducing new ones, and porting all the SW. This is where things go TILT. A processor has an eco-system where every level makes money (HW, SW tools, SW apps). Not so in an NPU space (SW comes for free as the sell is at the application level).
* Why ? – Others & I surmised that this was due to the market size issue. NPUs have broader applicability to the application spaces compared to ASSPs but they carry all the costs of a processor development without the associated market/eco-system to defray on-going costs. This is why many go to MIPS/ARM, otherwise a company would need to carry the NPU “eco-system” burden.
As Moore’s law rolls along it also opens up markets for commodity technologies (as you suggest) and closes markets for Application specific technologies. I see the NPU as just another technology node sandwiched in between ASSPs (early gens) and CPUs & FPGAs (next gens) that are addressing the same applications.
* So how does a Cavium make money ?
Stop thinking as a chip guy and start thinking as an application guy or a technology guy. To succeed, the apps guy needs to “surf” the waves of technology that can address a specific application. The end-game here is an application SW stack and some of the waves may be hard to transition.
A technology guy pushes his technology into the niches that Moore’s law opens up for him. Security, Parsing, home networking, … and adapts the peripherals and capabilities. Here the challenge is doubling the # of markets addressed by a specific tech node to keep up with costs.
A hybrid model exists, where application knowledge is transferred into a space where a new technology can be developed. I am interested as to how this actually plays out. Basically taking networking knowledge developed in the mid 90s and applying it to the home network of the late 2000s. Both networks probably have the same level of complexity. I suspect there are a lot of these application transition opportunities are available. What do you want in your home that only exists in your office? What would an enterprise guy want that only exists in the Aerospace/Defence industry. What do you want on your person that only exists in a stationary format today.
* Back to Cavium – I am assuming that the days of the native market (the one they started out in) doubling to keep pace with moores law are over.
Other good news for Cavium is that many vendors have exited the high-end MIPS marketplace.
Either way some fancy footwork is needed to survive.